Espressif Systems /ESP32-S2 /RMT /INT_ST

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Interpret as INT_ST

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH2_TX_END)CH2_TX_END 0 (CH0_RX_END)CH0_RX_END 0 (CH0_ERR)CH0_ERR 0 (CH1_TX_THR_EVENT)CH1_TX_THR_EVENT 0 (CH0_TX_LOOP)CH0_TX_LOOP

Description

Masked interrupt status

Fields

CH1_TX_END

The masked interrupt status bit for CH1_TX_END_INT.

CH0_TX_END

The masked interrupt status bit for CH0_TX_END_INT.

CH3_TX_END

The masked interrupt status bit for CH3_TX_END_INT.

CH2_TX_END

The masked interrupt status bit for CH2_TX_END_INT.

CH2_RX_END

The masked interrupt status bit for CH2_RX_END_INT.

CH1_RX_END

The masked interrupt status bit for CH1_RX_END_INT.

CH3_RX_END

The masked interrupt status bit for CH3_RX_END_INT.

CH0_RX_END

The masked interrupt status bit for CH0_RX_END_INT.

CH2_ERR

The masked interrupt status bit for CH2_ERR_INT.

CH3_ERR

The masked interrupt status bit for CH3_ERR_INT.

CH1_ERR

The masked interrupt status bit for CH1_ERR_INT.

CH0_ERR

The masked interrupt status bit for CH0_ERR_INT.

CH2_TX_THR_EVENT

The masked interrupt status bit for CH2_TX_THR_EVENT_INT.

CH3_TX_THR_EVENT

The masked interrupt status bit for CH3_TX_THR_EVENT_INT.

CH0_TX_THR_EVENT

The masked interrupt status bit for CH0_TX_THR_EVENT_INT.

CH1_TX_THR_EVENT

The masked interrupt status bit for CH1_TX_THR_EVENT_INT.

CH2_TX_LOOP

The masked interrupt status bit for CH2_TX_LOOP_INT.

CH1_TX_LOOP

The masked interrupt status bit for CH1_TX_LOOP_INT.

CH3_TX_LOOP

The masked interrupt status bit for CH3_TX_LOOP_INT.

CH0_TX_LOOP

The masked interrupt status bit for CH0_TX_LOOP_INT.

Links

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