Masked interrupt status
| CH0_TX_END | The masked interrupt status bit for CH0_TX_END_INT. |
| CH1_TX_END | The masked interrupt status bit for CH1_TX_END_INT. |
| CH2_TX_END | The masked interrupt status bit for CH2_TX_END_INT. |
| CH3_TX_END | The masked interrupt status bit for CH3_TX_END_INT. |
| CH1_RX_END | The masked interrupt status bit for CH1_RX_END_INT. |
| CH2_RX_END | The masked interrupt status bit for CH2_RX_END_INT. |
| CH0_RX_END | The masked interrupt status bit for CH0_RX_END_INT. |
| CH3_RX_END | The masked interrupt status bit for CH3_RX_END_INT. |
| CH3_ERR | The masked interrupt status bit for CH3_ERR_INT. |
| CH0_ERR | The masked interrupt status bit for CH0_ERR_INT. |
| CH2_ERR | The masked interrupt status bit for CH2_ERR_INT. |
| CH1_ERR | The masked interrupt status bit for CH1_ERR_INT. |
| CH1_TX_THR_EVENT | The masked interrupt status bit for CH1_TX_THR_EVENT_INT. |
| CH0_TX_THR_EVENT | The masked interrupt status bit for CH0_TX_THR_EVENT_INT. |
| CH3_TX_THR_EVENT | The masked interrupt status bit for CH3_TX_THR_EVENT_INT. |
| CH2_TX_THR_EVENT | The masked interrupt status bit for CH2_TX_THR_EVENT_INT. |
| CH2_TX_LOOP | The masked interrupt status bit for CH2_TX_LOOP_INT. |
| CH0_TX_LOOP | The masked interrupt status bit for CH0_TX_LOOP_INT. |
| CH3_TX_LOOP | The masked interrupt status bit for CH3_TX_LOOP_INT. |
| CH1_TX_LOOP | The masked interrupt status bit for CH1_TX_LOOP_INT. |